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About Us

Xceler Neuro-Morphic Engines and System Solutions provide the muscle for Low Power Edge Solutions to run Machine-Learning and AI Algorithms
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FPGA implementation of the Graph Engine provide an average of 6 x speedup (Running at 100 MHz) over the same program running on 32-bit ARM processors running at 1 GHz

For specific applications such as BLAS routines and DSP routines the speedup is several orders of magnitude over regular processors and DSP

Our Technology
  • Easy to Use

    • Adaptive, Programmable
    • Standard Programming languages and design entry (C/C++, python in future)
  • Unique architecture

    • Array of interconnected cells/neurons
    • No need for a supervisor or control processor in most applications
    • Field Programmable Neuromorphic Array
  • Low Power High Performance

    • Implement as a co-processor to ARM (AXI), RISC V or x86 (QPI) in FPGA or ASIC
    • Low power consumption less than 2W for typical implementation
    • Expendable using multiple instances
    • Low and deterministic latency

Potential Applications

Our Products