Neurons in the brain come in different types, based on the function and the location. Every Neuron on the brain shares some fundamental characteristics: it is an element that can compute, store and communicate. The communication between the Neurons takes place through dendrites that connect the nerve cells. The information that is communicated can take several forms, i.e. it could be computed locally by the Neuron, or a message relayed after “conditioning,” such as in the case of motor Neurons.
The fundamental building block of the Xceler processor is the “Digital Neuron.” These Digital Neurons form synapses with each other dynamically or statically based on the computational context. Just like in the Human Brain, some of the synapses are statically formed (memory and inferencing type functions) and some are dynamically formed (computation functions).
In the Xceler Engine Neurons can be intermixed with custom computation blocks and even small “ALU Like,” structures. Our patent pending parsing and scheduling technology that plugs into the back end of a standard compiler front end can take any standard program that is written in C/C++ or other high-level language and maps it to the engine.
The current incarnation of the Engine is the patent pending Xceler Graph Processor. The engine can run graphs generated by the forward compile flow for standard processors such as ARM, x86 and others.
Unlike the “Tensor,” processing units, multi-core processors and systolic array processors that generally work well with DAGs (Directed Acyclic Graphs), the Xceler Engine works like a processor that can execute complex non-planar graphs, loops etc. Our Non Von-neumann Architecture allows for a lot more flexibility on how we execute programs.
A graph or the sequence of actions (Sequencing Graph) in execution of an algorithm or a task has been in recent past dubbed as a “Tensor.” However at a program level the graphs are not DAGs (Directed Acyclic Graphs) but complex non-planar graphs with multiple nodes and interconnects. The Xceler architecture is able to exploit both spatial and temporal characteristics of the sequencing and control flow graphs.
The Xceler Architecture, based on the instance size forms between 100 million to 1 trillion unique synapses per second to perform computation. Multiple engines can be interconnected to form a large “Neural Farms” to accomplish complex Neural behaviors